Currently, one of the microelectronics industry's main demands is an increase in circuit density. This means that devices have to be scaled to continuously smaller dimensions. Shrinking transistor feature size necessitates a decrease in the gate dielectric layer thickness, which reaches its practical limit in a conventional gate dielectric material, such as SiO2 or nitrogen-containing SiO2. Because insulation layer thicknesses of less than 2 nm are anticipated in the future, alternatives to conventional gate dielectric materials have to be considered. These materials are characterized by higher dielectric constants when compared to SiO2 (k=4), and have been referred to as high-k dielectric materials. Many dielectrics appear favorable in some property areas, but only few are promising with respect to all property requirements.
Initially, some of the potential gate dielectric candidates, such as Ta2O5, SrTiO3, and Al2O3, have been inspired by memory capacitor applications. It was, however, proved that the requirements for transistor applications are much more selective than for memory capacitors. Two key requirements for transistor applications include an extremely high quality of the dielectric-channel interface that can only be approached if the high-k dielectrics are compatible with Si; and that the material is able to withstand Complementary Metal Oxide Semiconductor (CMOS) processing conditions while it is in contact with Si.
Besides of these primary requirements, the integration criteria raise many issues. One of these issues is the selective removability of these almost chemically inert and often relatively hard high-k materials over the source/drain areas. So, both dry and wet removal of high-k materials hold significant challenges with respect to silicon recess. The difficulties in removing possible high-k candidates, as discussed in numerous publications, are enhanced by the fact that the process must be selective to the other layers that are included in the device.
In device applications, the high-k material is mostly thermally treated, making it very resistant to standard wet chemistries, and therefore difficult to remove selectively towards oxide layers. For as-deposited dielectric layers, dilute HF solutions are often used because of their relatively high etch rate. Substantially lower etch rates are observed for thermally treated layers. Nevertheless, the main constraint is not the etch rate but the poor selectivity towards SiO2 and silicon layers.
As presented at the SPWC conference February 2003, California, Daikin reports on selective wet etching of high-k material by using an organic compound/25% HF mixture. The best selectivity reported is 1.7 for heat-treated Metal Organic Chemical Vapor Deposition (MOCVD) HfO2 towards thermal oxide. The highest etch rate for HfO2 is about 1 nm/min, also after annealing. The desired selectivity of 3:1 for thermally treated high-k towards oxide is not reached with their chemistry.
J. Barnett reports in the Proceedings of UCPSS 2002 (Solid State Phenomena, Vol. 92, p. 11, 2003), on the wet etch enhancement of HfO2 films by implant processing. However, the etch rate for a 20 nm HfO2 layer with hot phosphoric acid (155° C.) is only 0.12 nm/min. Other than the low etch rate, no results on selectivity towards other layers are presented. Also, the last monolayer of HfO2 seems not to be removable with hot phosphoric acid.
Mitsuhashi et al. report in U.S. Publication No. 2003-0104706-A1 a method for wet-etching metal oxides. The surface of the metal oxide film is exposed to a plasma, and the exposed metal oxide is then removed by a fluorine-containing solution. However, nothing is mentioned about selectivity towards SiO2, polysilicon, or silicon.
K. Saenger reports in the MRS Symposium Proceedings, Volume 745 (Novel Materials and Processes for advanced CMOS, Pennsylvania, p. 79, 2003) a selective etching process for chemically inert high-k metal oxides. The method used is ion bombardment supplied by an oxygen plasma in a reactive ion etching tool. Avoidance of oxygen treatments is recommended in order not to alter high-k layer characteristics by oxygen diffusion.
K. Christenson reports in Proceedings of UCPSS 2002 (Solid State Phenomena, Vol. 92, p. 129, 2003) the selective wet etching of high-k gate dielectrics. Only selectivity towards SiO2, and not selectivity towards silicon or polysilicon, is reported.